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? semiconductor components industries, llc, 2011 june, 2011 ? rev. 0 1 publication order number: NCP1927/d NCP1927 combination power factor correction controller and flyback controller for flat panel tvs this combination ic integrates the primary side control blocks ? power factor correction (pfc) and flyback controllers with sequencing circuitry ? necessary to implement a compact highly efficient flat panel tv switched mode power supply. the pfc controller exhibits near ? unity power factor while operating in critical conduction mode (crm) with an internal frequency clamp. the circuit incorporates all the features necessary for building a robust and compact pfc stage while minimizing the number of external components. the fixed ? frequency current ? mode flyback controller features a proprietary soft ? skip ? mode combined with frequency foldback enabling excellent efficiency during light load conditions while achieving very low standby power consumption. soft ? skip dramatically reduces the risk of acoustic noise, therefore enabling the use of inexpensive transformers and capacitors in the clamping network. frequency jittering and ramp compensation make this controller an excellent fit for converters where ruggedness and component cost are the key constraints. common general features ? wide v cc range from 10 v to 30 v ? very low startup current consumption ( 20 a max) ? inverter enable output ? shutdown pin to disable ic ? go to standby input ? this is a pb ? free device pfc controller features ? critical conduction mode (crm) with constant on time control ? internal frequency clamp ? skip mode operation during light load conditions ? fast line / load transient compensation ? accurate and programmable maximum on time control ? negative current sensing ? programmable overvoltage/undervoltage protection ? 800 ma source / 1200 ma sink gate drive flyback controller features ? 65 khz fixed ? frequency operation with built ? in ramp compensation ? frequency jittering for softened emi signature ? frequency foldback then soft ? skip for improved performance in standby ? timer ? based overload protection with auto ? recovery ? protection against winding short ? circuit ? 4 ms soft ? start timer ? 800 ma source / 1200 ma sink gate drive http://onsemi.com soic ? 16 case 751b marking diagram povuv pfb shutdown pcontrol pct pzcd pcs gts ienable pskip pdrv vcc fdrv gnd ffb fcs a = assembly location wl = wafer lot y = year ww = work week g = pb ? free package NCP1927 awlywwg device package shipping ? ordering information NCP1927dr2g soic ? 16 (pb ? free) 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specifications brochure, brd8011/d.
NCP1927 http://onsemi.com 2 figure 1. typical application example ovp hv to inverter 5.3 v standby 5.3v 13 v line input pskip ienable pdrv v cc fdrv gnd ffb fcs shutdown pfb povuv pcs pzcd gts c1 c2 r3 r6 d6 r4 r5 t1 d1 r17 r18 c9 c8 d4 d5 r26 d7 r25 r28 r23 c11 c10 r16 r15 r11 r10 r9 r8 r14 d8 d9 c4 c3 c5 c6 r33 r32 db1 q1 q2 d2 t2 r7 f1 l1 l2 cx1 cx2 r1 r2 r27 r22 r21 c12 d3 r29 r30 c14 c15 NCP1927 u1 u5 inverter enable r24 u4 u3 u6 cy1 zd1 on / off on / off c7 vcc_aux vcc_aux vcc_aux r19 on / off c13 pcontrol pct 13 v l3 l4
NCP1927 http://onsemi.com 3 figure 2. internal block diagram ffb s r q r q r s r q drv zcd clk 30 s filter 30 s filter 30 s filter start_delay pfc_ok pdrv pdrv pdrv start_delay 5v reg clamp v dd v dd v cc r 9*r pfc fault management v shdn v uvp v ovp v ref 0.955*v ref v zcd(rising) v zcd(falling) pfault ffault ovp_int ovp_int pfault pfc_ok i pcontrol(boost) i pcs > i ocp pfc_ok i pskip v dd v standby flyback_ovld v cc & latch management v cc(on) v cc(off) v cc(reset) v dd v dd reg latch shutdown 30 s filter tsd ffault s q r clamp v cc osc soft ? skip timer leb ffault v ffb(open) ss_enable cs_stop saw saw saw r ffb v fskip v ilim leb cs_stop v cs(stop) r ramp latch shutdown v ilim saw square reset skip out saw in i pct(charge) i uvp r gts pfault 10 s filter ffault timer reset flyback_ovld 5 s v disable 30 s filter start_delay wdt reset pdrv frequency clamp r t on(max) timer jittering ss_end frequency foldback pfm fm ffault s q r soft ? start timer ss_enable ss_end ramp 0 a detect i shutdown v dd shutdown ienable pdrv v cc ffb fcs fdrv gnd povuv pfb pcontrol pct pzcd pcs pskip gts gos timer gts timer * values are typical values * all latches are reset dominant
NCP1927 http://onsemi.com 4 pin function description pin no. pin name pin description 1 povuv the gate drive is disabled while v povuv is below v uvp (300 mv typ) or above v ovp (2.5 v typ). 2 pfb this pin receives a portion of the pre ? converter output voltage. this information is used for the regulation and the ?output low? detection that speeds up the loop response when the output voltage drops below 95.5% (typ) of the programmed level. 3 shutdown pull this pin above 1.0 v (typ) to disable the part. ground this pin when not in use. 4 pcontrol the error amplifier output is available on this pin. the capacitor connected between this pin and ground adjusts the regulation loop bandwidth that is typically set below 20 hz to achieve a high power factor. this pin is internally grounded when the circuit is off so that when it starts operation, the power increases gradually (soft ? start). 5 pct the pct pin sources a 210 a (typ) current to charge an external timing capacitor. the circuit controls the power switch on time by comparing the pct voltage to an internal voltage derived from the regulation block. 6 pzcd the voltage of an auxiliary winding is applied to this pin to detect when the inductor is demagnetized for operation in critical conduction mode. 7 pcs this pin monitors a negative voltage proportional to the coil current. this signal is sensed to limit the maximum coil current and protect the pfc stage during overload conditions. 8 gts pull this pin low to disable the pfc controller during standby mode. standby mode can also be entered by monitoring the feedback voltage of the flyback stage with an external resistor divider. 9 fcs this pin senses the primary current for current ? mode operation of the flyback stage. ramp compensation can be added with an external resistor. 10 ffb connecting this pin to ground through an optocoupler allows regulation of the flyback stage. 11 gnd this is the the controller ground. 12 fdrv this is the driver?s output to an external mosfet gate of the flyback power stage. 13 v cc this pin is connected to an external auxiliary voltage. 14 pdrv this is the driver?s output to an external mosfet gate of the pfc power stage. 15 pskip to adjust the power level below which the pfc stage will enter skip mode, connect a resistor between this pin and ground. to disable skip mode, connect this pin directly to ground. 16 ienable this pin voltage is high (5 v) when the output of the pfc stage is in steady state regulation and low at all other times. this signal serves to ?inform? the backlight inverter that the pfc output is ready and that it can start operation. it can also be used as a stable 5 v reference.
NCP1927 http://onsemi.com 5 maximum ratings (note 1) rating symbol value unit supply pin (pin 13) (note 2) voltage range current range v cc(max) i cc(max) ? 0.3 to 30 30 v ma pfc drive pin (pin 14) (note 2) voltage range current range v pdrv(max) i pdrv(max) ? 0.3 to 20 ? 800, +1200 v ma flyback drive pin (pin 12) (note 2) voltage range current range v fdrv(max) i fdrv(max) ? 0.3 to 20 ? 800, +1200 v ma inverter enable pin (pin 16) (note 2) voltage range current range v ienable(max) i ienable(max) ? 0.3 to 6 20 v ma control pin (pin 4) (note 2) voltage range current range v pcontrol(max) i pcontrol(max) ? 0.3 to 6 10 v ma pfc current sense pin (pin 7) (note 2) voltage range current range v pcs(max) i pcs(max) ? 0.3 to 3 10 v ma zcd pin (pin 6) (note 2) voltage range current range v pzcd(max) i pzcd(max) ? 0.9 to 12 10 v ma all other pins (note 2) voltage range current range v max i max ? 0.3 to 10 10 v ma thermal resistance junction ? to ? air, 100 mm 2 single layer of 1 oz copper r ja 140 c/w temperature range storage temperature operating junction temperature t jstrg(max) t j(max) ? 60 to 150 ? 25 to 125 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. this device series contains esd protection and exceeds the following tests: charged device model 2000 v per jedec standard jesd22-c101d human body model 2000 v per jedec standard jesd22 ? a114e machine model 200 v per jedec standard jesd22 ? a115a 2. this device contains latch ? up protection and exceeds 100 ma per jedec standard jesd78.
NCP1927 http://onsemi.com 6 electrical characteristics (v cc = 12 v, v pfb = 2.4 v, v povuv = 2.3 v, v pcontrol = 4 v, v pzcd = 0 v, v pcs = 0 v, v gts = 1 v, v pskip = 0 v, v ffb = 2.4 v, v fcs = 0 v, v shutdown = 0 v, v ienable = open, c pct = 1 nf, c pdrv = 1 nf, c fdrv = 1 nf, for typical values t j = 25 c, for min/max values, t j is ? 25 c to 125 c, unless otherwise noted) characteristics test condition symbol min typ max unit supply circuit supply voltage startup threshold minimum operating voltage internal latch reset level v cc increasing, dv/dt = 1.25 mv/ s v cc decreasing, dv/dt = 125 v/ s v cc decreasing v cc(on) v cc(off) v cc(reset) 16 8 5.0 17 9 6.5 18 10 8.0 v supply current pfc is switching at 70khz pfc is switching at 70khz flyback switching, pfc is in gts during faults startup c fdrv = open, c pdrv = open v ffb = v fold ? 0.2 v, c fdrv = open, v fcs = 0.8 v v cc = v cc(on) ? 0.2 v i cc1 i cc2 i cc3 i cc4 i cc5 2.4 3.8 1.0 1.0 ? 3.3 5.1 1.5 1.5 ? 4.2 6.4 2.0 2.5 20 ma ma ma ma a flyback feedback equivalent internal pull ? up resistor r ffb 14 20 31 k v ffb to internal current setpoint division ratio k ffb 4.8 5.0 5.2 overload detection filter t delay(fovld) ? 10 ? s flyback fault timer v ffb = 4.5 v to fdrv turn ? off t fovld 60 80 100 ms ffb pin voltage v ffb = open v ffb(open) 4.5 5.0 5.5 v flyback current sense current sense voltage threshold v ffb = 4.5 v v ilim 0.655 0.700 0.725 v leading edge blanking duration t leb 190 250 310 ns propagation delay current sense voltage threshold immediate fault protection step v fcs 0 v to 2 v, to fdrv falling edge t delay(ilim) t cs(stop) ? ? 80 80 110 110 ns ns immediate fault protection threshold v ffb = 3 v, v fcs dv/dt = 500 v/ s v cs(stop) 0.95 1.05 1.15 v leading edge blanking duration for i cs(stop) t leb(stop) 90 120 150 ns input bias current v fcs = v ilim i fcs(bias) ? 1 ? +1 a current sourced by the fcs pin v fcs = 0 v, 80% duty ratio i ramp(max) 100 150 200 a flyback soft ? start soft ? start period 1 st fdrv pulse to v fcs = v ilim t sstart 2.8 4.0 5.2 ms oscillator base oscillator frequency f osc 60 65 70 khz maximum duty ratio d max 76 80 84 % frequency modulation in percentage of f osc f mod ? 6 ? % frequency modulation frequency f jitter ? 125 ? hz oscillator frequency voltage stability v cc(min) < v cc < v cc(max) f osc(vstab) ? 1 ? +1 %
NCP1927 http://onsemi.com 7 electrical characteristics (v cc = 12 v, v pfb = 2.4 v, v povuv = 2.3 v, v pcontrol = 4 v, v pzcd = 0 v, v pcs = 0 v, v gts = 1 v, v pskip = 0 v, v ffb = 2.4 v, v fcs = 0 v, v shutdown = 0 v, v ienable = open, c pct = 1 nf, c pdrv = 1 nf, c fdrv = 1 nf, for typical values t j = 25 c, for min/max values, t j is ? 25 c to 125 c, unless otherwise noted) characteristics unit max typ min symbol test condition flyback gate drive fdrv impedance sink source v fdrv = 10 v v fdrv = 2 v r fdrv(snk) r fdrv(src) ? ? 12.5 14 ? ? fdrv rise time (10% to 90%) t fdrv(r) 15 30 80 ns fdrv fall time (90% to 10%) t fdrv(f) 12 25 70 ns fdrv low voltage i fdrv = 0 ma v fdrv(low) ? 0.06 0.5 v fdrv voltage drop v cc = v cc(off) + 0.2 v, r fdrv = 33 k v fdrv(drop) ? ? 1 v fdrv clamp voltage v cc = 30 v, i fdrv = 0 ma v fdrv(clamp) 11 13.5 16 v flyback skip mode/freq foldback skip threshold v ffb decreasing v fskip 630 700 770 mv skip comparator hysteresis v fskip(hys) 65 100 135 mv soft ? skip duration 1 st pulse to v fcs = v fold /k ffb t sskip 50 100 140 s frequency foldback threshold v ffb decreasing, dv/dt = 500 v/ s v fold 1.26 1.40 1.54 v minimum switching frequency v ffb = v fskip + 150 mv f osc(min) 21 26 31 khz maximum on time frequency foldback or skip mode t on(max) 10.0 13.0 16.0 s pfc current sense pcs pin voltage r pcs = 2.5 k , i pcs = 265 a v pcs ? 20 0 20 mv overcurrent protection threshold r pcs = 2.5 k i ocp 230 250 265 a propagation delay step i pcs 0 a to 400 a i ocp to pdrv falling edge r pcs = 1 k t ocp ? 100 210 ns pfc ramp control pct charge current v pct = 1.5 v i pct(charge) 189 210 231 a c pct discharge time v pcontrol = open, c pcontrol = 10 nf v pct = v pct(max) ? 100 mv to 600 mv t cpct(discharge) ? ? 500 ns maximum pct level before pdrv switches off v pcontrol = open, c pcontrol = 10 nf v pct(max) 4.7 5.0 5.3 v propagation delay of the pwm comparator step v pct from 3.5 v to 5.0 v t pwm ? 150 200 ns pfc frequency clamp f clamp 330 385 440 khz pfc gate drive pdrv impedance sink source v pdrv = 10 v v pdrv = 2 v r pdrv(snk) r pdrv(src) ? ? 12.5 14 ? ? pdrv rise time (10 % to 90 %) t pdrv(r) 15 30 80 ns pdrv fall time (90 % to 10 %) t pdrv(f) 12 25 70 ns pdrv low voltage i pdrv = 0 ma v pdrv(low) ? 0.06 0.5 v pdrv voltage drop v cc = v cc(off) + 0.2 v, r pdrv = 33 k v pdrv(drop) ? ? 1 v pdrv clamp voltage v cc = 30 v, i pdrv = 0 ma v pdrv(clamp) 11 13.5 16 v
NCP1927 http://onsemi.com 8 electrical characteristics (v cc = 12 v, v pfb = 2.4 v, v povuv = 2.3 v, v pcontrol = 4 v, v pzcd = 0 v, v pcs = 0 v, v gts = 1 v, v pskip = 0 v, v ffb = 2.4 v, v fcs = 0 v, v shutdown = 0 v, v ienable = open, c pct = 1 nf, c pdrv = 1 nf, c fdrv = 1 nf, for typical values t j = 25 c, for min/max values, t j is ? 25 c to 125 c, unless otherwise noted) characteristics unit max typ min symbol test condition pfc zero current detection zero current detection threshold rising falling v zcd(rising) v zcd(falling) 1.12 0.56 1.40 0.70 1.68 0.84 v hysteresis on voltage threshold v zcd(rising) ? v zcd(falling) v zcd(hys) 560 700 840 mv propagation delay step v pzcd from 2 v to 0 v t zcd ? 100 170 ns clamp voltage upper clamp negative clamp i pzcd = 3 ma i pzcd = ? 2 ma v cl(pos) v cl(neg) 8 ? 0.9 10 ? 0.7 12 0 v minimum detectable zcd pulse width t sync ? 70 100 ns maximum off time pdrv off = 10% to pdrv on = 90% t start 75 180 300 s input bias current v pzcd = 5 v v pzcd = ? 0.2 v i pzcd(bias) i pzcd(bias) ? 2 ? 2 ? ? 2 2 a a pfc skip mode skip pin internal current source i pskip 27 30 33 a hysteresis of the skip cycle detection level v pskip = 1 v v pskip(hys) 10 12 16 % pfc regulation block voltage reference v ref 2.463 2.500 2.537 v error amplifier current capability maximum source current maximum sink current v pfb = 2.4 v, v povuv = 3 v v pfb = 2.6 v, v povuv = 3 v i ea(src) i ea(snk) 16 16 20 20 24 24 a a error amplifier transconductance v pfb = v ref 100 mv, v povuv = 3 v gm 100 200 300 s pfb bias current v pfb = 2.5 v i pfb(bias) ? 0.5 ? 0.5 a maximum ea output voltage v pfb = 2 v v pcontrol = open, c pcontrol = 10 nf v pcontrol(max) 5.05 5.6 6.1 v minimum ea output voltage v pfb = 3 v v pcontrol = open, c pcontrol = 10 nf v pcontrol(min) 0.35 0.6 0.8 v ea output regulation voltage swing v pcontrol(max) ? v pcontrol(min) v pcontrol 4.7 5.0 5.3 v ratio (v out low detect threshold / v ref ) v olow /v ref 95.0 95.5 96.0 % v out low detect / v ref hysteresis v olow(hys) / v ref ? ? 1.0 % source current during v out low detect i pcontrol(boost) 190 240 290 a go to standby (gts) internal pull ? down resistor r gts 80 200 320 k standby threshold v gts decreasing v standby 270 300 330 mv standby hysteresis v standby(hys) 85 100 125 mv go to standby timer step v gts from 1 v to 0 v step v gts from 0 v to 1 v t gts(off) t gts(on) 37.5 30 50.0 50 62.5 70 ms s
NCP1927 http://onsemi.com 9 electrical characteristics (v cc = 12 v, v pfb = 2.4 v, v povuv = 2.3 v, v pcontrol = 4 v, v pzcd = 0 v, v pcs = 0 v, v gts = 1 v, v pskip = 0 v, v ffb = 2.4 v, v fcs = 0 v, v shutdown = 0 v, v ienable = open, c pct = 1 nf, c pdrv = 1 nf, c fdrv = 1 nf, for typical values t j = 25 c, for min/max values, t j is ? 25 c to 125 c, unless otherwise noted) characteristics unit max typ min symbol test condition pfc fault protection overvoltage protection threshold v ovp 2.450 2.500 2.550 v overvoltage protection hysteresis v ovp(hys) 20 40 60 mv overvoltage protection filter delay t delay(ovp) ? 30 ? s undervoltage protection threshold v uvp 285 300 315 mv undervoltage protection hysteresis v uvp(hys) 20 40 60 mv undervoltage protection filter delay t delay(uvp) ? 30 ? s uvp pull down current source i uvp 0.7 1.0 1.3 a ratio between v ovp and v ref (note 3) v ovp /v ref 99.5 100.0 100.5 % inverter enable/reference disable threshold v disable 1.809 1.865 1.921 v disable filter delay t delay(disable) ? 30 ? s voltage reference i ienable(src) = 8 ma i ienable(src) = 1 ma i ienable(snk) = 250 a v ienable(high) v ienable(high) v ienable(low) 4.5 4.7 ? 5.0 5.0 60 5.4 5.4 120 v v mv reference pin decoupling capacitor c ref 0 ? 1 f thermal protection thermal shutdown t tshdn ? 150 ? c thermal shutdown delay t delay(tshdn) ? 30 ? s shutdown pin shutdown threshold v shutdown increasing v shdn 0.90 1.00 1.10 v shutdown filter delay v shutdown increasing t delay(shdn) ? 30 ? s pull up current source i shutdown 2.3 3.3 4.3 a 3. guaranteed by design
NCP1927 http://onsemi.com 10 detailed operating description introduction the NCP1927 is a combination power factor correction (pfc) and flyback controller optimized for use in flat panel tvs. this device includes all the features needed to implement a highly efficient and compact power supply. it integrates a critical conduction mode (crm) pfc controller and a fixed ? frequency current mode flyback controller with proper sequencing for simplified system design. this device includes frequency jittering, a shutdown input, an inverter enable output, a go to standby input, and a dedicated pin for under/overvoltage protection. supply sequencing the flyback controller of the NCP1927 is enabled once v cc reaches v cc(on) , provided it is not in thermal shutdown and has not been latched off or shutdown. once the flyback controller is enabled, a soft ? start timer is activated, and it begins switching. the soft ? start timer provides a ramp signal that increases over t sstart (typically 4.0 ms). this ensures that the peak current gradually increases to minimize power component stress and limit output voltage overshoot. frequency jittering is disabled while the soft ? start timer is running. once the flyback controller detects regulation on the output (it is no longer in overload), the pfc controller can be enabled. as soon as the pfc controller is enabled, the error amplifier begins to source its maximum output current, i ea(max) , (typically 20 a) to linearly charge the pcontrol pin capacitor (c pcontrol ). soft ? start is achieved as c pcontrol charges. an internal grounding switch on the pcontrol pin is turned on each time the pfc controller is disabled, and turned off when it is enabled. this ensures that c pcontrol is always fully discharged at the beginning of soft ? start. as the pfc stage approaches regulation on the output, the error amplifier output current, i ea , gradually reduces to 0 a. once the output is in regulation and i ea reaches 0 a, the ienable pin is set to v ienable(high) (typically 5 v). v cc management when power is initially applied to the application, the v cc capacitor (c vcc ) begins charging through a resistor connected to the high voltage line (v in ). the resistor value must be chosen so that the charging current is greater than the ic bias current during startup. the maximum value for the startup resistor is calculated using equation 1. r start v in i cc5 (eq. 1) where v in is the rectified dc input voltage and i cc5 is the ic bias current during startup (20 a maximum). when v cc reaches v cc(reset) (typically 6.5 v), a power on reset occurs. this resets all logic states on the device. as v cc continues to rise, the ic bias current remains at i cc5 until v cc reaches v cc(on) (typically 17 v). once v cc reaches v cc(on) , the flyback controller is enabled and the ic bias current increases to i cc3 (1.5 ma typical). however, the total i cc current is greater than this due to the gate charge load at the flyback drive output (fdrv). once the flyback is in regulation, the pfc controller can be enabled. when the pfc is enabled, the i cc current increases further due to the gate charge load at the pfc drive output (pdrv). the increase in i cc per mosfet is calculated using equation 2. i cc(x) f osc q g(x) (eq. 2) where, f osc is the switching frequency and q g( x) is the gate charge of the external mosfet x . c vcc must be sized such that a v cc voltage greater than v cc(off) (9 v typical) is maintained while the auxiliary supply voltage increases during startup. if c vcc is too small, v cc falls below v cc(off) and the controller turns off before the auxiliary winding powers up the controller. the total i cc current after the flyback controller is enabled (i cc3 plus i cc(fdrv) ) must be considered to correctly size c vcc . it is often useful to connect a small v cc capacitor (c1) directly to the v cc pin, while a larger capacitor (c2) is connected to the v cc pin through a diode and charged by the aux winding. this allows minimum startup time while providing enough v cc capacitance to operate during light load conditions. this implementation is shown in figure 3 and the startup sequence is shown in figure 4.
NCP1927 http://onsemi.com 11 figure 3. operation with dual v cc capacitors i cc r start d1 d2 c1 c2 v in aux winding v cc NCP1927 ++ figure 4. startup sequence of the NCP1927 time pdrv fdrv time v cc(on) v cc(off) v cc(reset) 0 v time i cc5 i cc3 + icc(fdrv) i cc1 +i cc(fdrv) +i cc(pdrv) v cc drv i cc pdrv fdrv fault management when the NCP1927 detects a non ? latching fault (shutdown mode, tsd, and flyback overload), the drivers are disabled, and v cc falls towards v cc(off) due to the ic internal current consumption. once v cc falls below v cc(off) , the fault is reset and the ic internal current consumption is reduced to the startup current, i cc5 . v cc begins to rise as if power was initially applied and the device resumes normal operation once v cc reaches v cc(on) . this cycle between v cc(on) and v cc(off) is commonly referred to as a v cc hiccup and is shown in figure 5. figure 5. v cc during a v cc hiccup time v cc time drv v cc on v cc off device restarts fault occurs fault is reset time i cc i cc 4 i cc 5 i cc 2 shutdown pin the shutdown pin allows for external disabling of the NCP1927. when v shutdown is pulled above the shutdown threshold, v shdn (typically 1.0 v), both the flyback and pfc drive outputs are immediately turned off, and a v cc hiccup occurs (see figure 5). when v cc reaches v cc(on) , the cycle repeats unless the NCP1927 is taken out of shutdown. this is achieved when v shutdown becomes less than v shdn . the NCP1927 leaves shutdown mode and will start when v cc reaches v cc(on) according to the initial power ? on sequence. the v cc behavior during shutdown mode is shown in figure 6.
NCP1927 http://onsemi.com 12 figure 6. v cc behavior during shutdown mode thermal shutdown when the junction temperature exceeds t tshdn (140 c minimum), a temperature sensing circuit disables the gate drives and a v cc hiccup occurs (see figure 5). when v cc reaches v cc(on) , the cycle repeats unless the junction temperature drops below t tshdn . clamped drivers the NCP1927 includes two powerful mosfet drivers capable of sourcing 800 ma and sinking 1200 ma each. since v cc is rated at 30 v (maximum), each driver output is internally clamped to 16 v (maximum) to allow the use of 20 v mosfets. flyback controller the NCP1927 flyback stage implements a standard current mode architecture where the switch ? off event is dictated by the peak current setpoint. oscillator with maximum duty ratio and frequency jittering the NCP1927 flyback controller includes an oscillator that sets the switching frequency with an accuracy of 7.7%. the maximum duty ratio of the fdrv pin is 80% (typical). in order to improve the emi signature, the switching frequency jitters at f mod ( 6% typical) around its nominal value, with a triangle ? wave shape and at a frequency of f jitter (125 hz typical). the frequency jittering is fully disabled during soft ? start and frequency foldback. figure 7 depicts the jittering operation. figure 7. frequency jittering time f osc + f mod 8 ms (125 hz) nominal f osc f osc - f mod f osc current sensing NCP1927 is a current ? mode controller, which means that the feedback voltage sets the peak current flowing in the transformer and the mosfet. this is done through the pwm comparator. the switch current is sensed across a resistor and the resulting voltage is applied to the fcs pin. it is then applied to one input of the pwm comparator through a 250 ns leading edge blanking (leb) block. on the other input, the feedback voltage divided by k ffb (typically 5) sets the current limit threshold. when the current reaches this threshold, the output driver is turned off. a dedicated comparator monitors the current sense voltage, and if it reaches the maximum value, v ilim (typically 0.7 v), the output driver is turned off immediately. this occurs even if the limit imposed by the feedback voltage is higher than v ilim . figure 8 shows the schematic of the current sense circuit. figure 8. current sense block schematic ffb v ffb(open) r ffb v ilim s qr v cc fdrv f (osc) fcs t leb k ffb
NCP1927 http://onsemi.com 13 short ? winding protection under some conditions, like a transformer winding or output diode short ? circuit, the primary current increases above v ilim before the leb timer expires. to prevent dangerously high current from flowing, an additional comparator senses when v fcs reaches v cs(stop) . once this comparator toggles, the controller immediately latches off. the effect of latching off the ic is identical to shutdown mode, however, the v cc cycle repeats indefinitely until the input power is removed and c vcc is allowed to discharge below v cc(reset) . when input power is reapplied, the NCP1927 operates according to the initial power ? on sequence. the v cc behavior during short winding protection is shown in figure 9. figure 9. v cc behavior during short winding protection time fcs pin time v cc time drv v cc(on) v cc(off) short winding detected v cs(stop) time i cc i cc4 i cc6 i cc2 feedback the ratio from the feedback voltage to the current limit threshold, k ffb (typically 5), determines the peak current limit threshold. this means that the feedback voltage when the current limit threshold equals v ilim is 3.5 v (typical). the ffb pin is connected to the internal v dd rail through a resistor divider. to ease system design, the ffb pin is represented by a thevenin equivalent circuit containing a voltage source and series resistor, v ffb(open) (typically 5 v) and r ffb (typically 20 k ). soft ? start the NCP1927 flyback controller features an internal soft ? start circuit. every time the controller starts (i.e. the controller was off and starts, or restarts due to a fault), a soft ? start is applied when v cc reaches v cc(on) . the current limit threshold is linearly increased from 0 until it reaches v ilim (in 4.0 ms), or until the feedback loop imposes a setpoint lower than the one imposed by the soft ? start (the 2 comparator outputs are or?ed together). figure 10 shows a typical startup sequence. figure 10. soft ? start timing time v fb time soft ? start ramp v ilim t sstart time cs setpoint v ilim v fb takes over soft ? start ramp compensation ramp compensation is a known method for preventing subharmonic oscillations. these oscillations take place at half the switching frequency and occur only during continuous conduction mode (ccm) when the duty ratio is greater than 50%. to prevent these oscillations, one typically lowers the current loop gain by injecting between 50% and 75% of the inductor downslope. this is done by inserting a resistor (r scomp ) between the fcs pin and the current sense resistor. figure 11 shows an example of this. the ramp signal is disconnected from the fcs pin during the off time. figure 11. inserting a resistor ? + on l.e.b. fdrv reset from ffb setpoint fcs r scomp i ramp i ramp(max) r sense 0 a
NCP1927 http://onsemi.com 14 when calculating the proper value for r scomp , it is necessary to express the internal ramp signal in terms of its slope (di osc /dt). this is done using equation 3. dl osc dt i ramp(max) f osc d max (eq. 3) the inductor downslope (dv p(off) /dt) projected across the current sense resistor (r sense ) is then calculated using equation 4. dv p(off) dt r sense v out v d n s n p l p (eq. 4) where v d is the forward drop of the output rectifier, n s /n p is the turns ratio, and l p is the primary inductance. using the results from equations 3 and 4, r scomp can be calculated using equation 5. r scomp dv p(off) dt di osc dt (eq. 5) where is the percentage of dv p(off) /dt to be injected. overload protection with fault timer when an overload occurs on the output of the power supply, the feedback loop asks for more power than the controller can deliver, and the current limit threshold reaches v ilim . when this event occurs, a fault timer (t fovld ) is enabled. when the timer expires, fdrv pulses are stopped, the pfc is disabled, and a v cc hiccup occurs. when v cc reaches v cc(on) , the controller starts according to the initial power ? on sequence. if the overload is still present, the fault timer continues to run and the cycle repeats when it expires. the fault timer is reset if the current limit threshold goes back below v ilim . a short delay, t delay(fovld) , is added to prevent the fault timer from resetting due to noise. this autorecovery operation is depicted in figure 12. figure 12. operation during overload time fault flag time v cc time drv v cc(on) v cc(off) overcurrent applied time output load max load time fault timer 80 ms fault timer starts controller stops fault disappears t fovld restart at v cc(on) fault is reset frequency foldback in order to improve the efficiency at light load conditions, the frequency of the internal oscillator is linearly reduced from its nominal value down to f osc(min) (typically 26 khz). the frequency foldback starts when the voltage on the ffb pin goes below v fold , and is completed before v ffb reaches v fskip . the current ? mode control remains active while the oscillator frequency decreases. this is shown in figure 13. figure 13. switching frequency as v ffb decreases ffb oscillator frequency f osc v fskip v fold f osc(min) skip skip cycle mode with soft ? skip when the feedback voltage reaches v fskip while decreasing, skip mode is activated and the driver stops switching. while the driver is disabled, v ffb begins to rise. as soon as v ffb rises above v fskip + v fskip(hys) , the driver starts to switch again, but the duty ratio is gradually increased from nearly 0% over a short soft ? skip duration (t sskip ). this is accomplished by comparing the current
NCP1927 http://onsemi.com 15 sense signal to an internal ramp generated by the soft ? skip timer instead of the feedback voltage. since the leb of the fcs pin prevents operation at nearly 0% duty ratio, the controller instead compares the soft ? skip ramp to an internal sawtooth signal generated by the oscillator (not subjected to leb). this causes the controller to operate briefly in voltage mode instead of current mode. once the cs signal reaches the feedback voltage, the controller resumes normal operation in current mode. the skip mode block diagram is shown in figure 14. the ramp timing and overall timing diagrams are shown in figures 15 and 16. figure 14. skip cycle with soft ? skip architecture fdrv stage fcs s r q soft ? skip ramp ffb reset oscillator sawtooth t leb k ffb v fskip d max v fskip t sskip + ? ? + figure 15. skip cycle with soft ? skip timing diagram time v ffb v fskip(hys) time fdrv time cs setpoint soft ? skip enters soft ? skip soft ? skip exits soft ? skip v fskip v fold during the soft ? skip duration if the feedback voltage goes above v fold , the soft ? skip ends instantaneously allowing the controller to operate in current mode. this transient load detection feature avoids large output drops if a load transient occurs while the controller is in skip mode. figure 16. soft ? skip timing diagram
NCP1927 http://onsemi.com 16 pfc controller the pfc stage operates in critical conduction mode (crm). crm occurs at the boundary between discontinuous conduction mode (dcm) and continuous conduction mode (ccm). in crm, the driver on time is initiated when the boost inductor current reaches zero. crm operation is an ideal choice for medium power pfc boost stages because it combines the lower peak currents of ccm operation with the zero current switching of dcm operation. the operation and waveforms in a pfc boost converter are illustrated in figure 17. figure 17. schematic and waveforms of an ideal crm boost converter diode bridge + ? l diode bridge + ? l + the power switch is on the power switch is off critical conduction mode: next current cycle starts as soon as the core is reset. coil current + the power switch being about zero, the input voltage is applied across the coil. the coil current linearly increases with a (v in /l) slope. the coil current flows through the diode. the coil voltage is (v out ? v in ) and the coil current linearly decays with a (v out ? v in )/l slope. i l v out v in v drain (v out ? v in )/l i l(peak) i l v in v drain v in /l v out v in if next cycle does not start then v drain rings towards v in + time time when the switch is closed, the inductor current increases linearly to its peak value. when the switch opens, the inductor current linearly decreases to zero. at this point, the drain voltage of the switch (v drain ) begins to drop. if the next switching cycle does not start, the voltage rings with a dampened frequency around vin. a simple derivation of equations (such as those found in and8123) leads to the result that good power factor correction in crm operation is achieved when the on time is constant across a single ac cycle. equation 6 shows the relationship between on time and system operating conditions. t on 2 p out l vac 2 (eq. 6) where p out is the output power, l is the boost inductor inductance and is the system efficiency. a plot of the mosfet on/off time over an ac line cycle is illustrated in figure 18. the mosfet off time varies based on the instantaneous line voltage, but the on time is constant. this causes the peak inductor current (i l(peak) ) to follow the ac line voltage. the NCP1927 implements constant on time crm control in a cost ? effective and robust manner. figure 18. inductor waveform during crm operation v in(peak) i l(peak) i in(peak) v in (t) i l (t) i in (t) on off mosfet time time
NCP1927 http://onsemi.com 17 output regulation the NCP1927 error amplifier (ea) consists of an operational transconductance amplifier (ota) with the inverting input connected to the pfb pin and the output connected to the pcontrol pin to regulate the output voltage. it features a typical transconductance (gm) of 200 s and a maximum output (i ea(src) and i ea(snk) ) of 20 a (typical). the non ? inverting input is connected internally to a voltage reference (v ref ) with a typical value of 2.5 v 1.5% over process and temperature. during normal operation, the voltage on the pcontrol pin varies between v pcontrol(min) (typically 0.6 v) and v pcontrol(max) (typically 5.6 v). a simplified diagram of the ota circuit is shown in figure 19. figure 19. error amplifier and on time regulation circuits c pcontrol a resistor divider from the boost output to the pfb pin provides a scaled ? down representation of the output voltage (v out ) to the ea. when v out is in regulation, v pfb equals v ref . if v out drops below regulation, the feedback voltage (v pfb ) drops and the ea sources current until v pfb returns towards v ref . this increases the control voltage (v pcontrol ) and the on time of the driver (t on ), which in turn increases the power delivered to the load and brings v out back into regulation. alternatively, if v out (and also v pfb ) is too high, the ea sinks current and v pcontrol decreases, thus shortening t on until v out returns to regulation. the output voltage is calculated using equation 7. v out v ref r pfb1 r pfb2 r pfb2 (eq. 7) where r pfb1 is the upper resistor of the resistor divider, and r pfb2 is the lower resistor. the impedance of the feedback network determines its noise immunity and power dissipation. while a lower impedance provides better noise immunity, it also increases power dissipation. once the divider current is chosen, r pfb1 is determined using equation 8. r pfb1 v out i divider (eq. 8) where i divider is the resistor divider current. using r pfb1 , r pfb2 is calculated with equation 9. r pfb2 r pfb1 v ref v out
v ref (eq. 9) compensation a compensation network must be connected between the pcontrol pin and ground due to the nature of an active pfc circuit. the pfc stage generates a sinusoidal current from the ac line voltage and provides the load with a power that matches the average demand. when the input voltage is at its peak, the pfc stage delivers more power than the load requires, and the output capacitor charges. conversely, when the input voltage is at a valley, the load requires more power than the pfc stage can deliver, and the output capacitor discharges. the situation is depicted in figure 20. figure 20. output voltage ripple for a constant output power time time time v out (t) p out (t) p in (t) v in (t) i in (t) this creates a ripple on the output with frequency equal to twice the line frequency (f line ). since the on time must remain constant during each ac line cycle to maintain good power factor correction, the ea must reject the output ripple. this is commonly achieved by setting the regulation bandwidth below 20 hz. a type 1 compensation network is typically used for simplicity, as it only requires a single capacitor (c pcontrol ) connected between the pcontrol pin and ground (see figure 19). for a type 1 network, c pcontrol is calculated using equation 10. c pcontrol gm 2 f c (eq. 10) where gm is the transconductance of the ea (typically 200 s) , and f c is the desired crossover frequency (typically less than 20 hz).
NCP1927 http://onsemi.com 18 transient load detection due to the low bandwidth of the regulation loop, fast load transients may result in output voltage over and undershoots. overshoots are limited by the overvoltage protection (see ovp section). to control the undershoots, an internal comparator monitors the ratio between v pfb and v ref . when it is lower than v olow /v ref (95.5% typical), i pcontrol(boost) (240 a typical) is connected to the pcontrol pin to speed up the charging of c pcontrol . this has the ef fect of increasing the ea gain by a factor of approximately 13. the transient load detection circuit is disabled during the startup sequence of the pfc stage to prevent it from interfering with the operation of the soft ? start circuit. on time control since the NCP1927 is designed to control a crm boost converter, the switching pattern consists of constant on times and variable off times. the on time is set via an external capacitor (c t ) connected to the pct pin. at the beginning of each switching cycle, c t is charged linearly by i pct(charge) (210 a typical). an internal comparator monitors the voltage on the pct pin (v pct ) and compares it to an internal regulation limit set by v pcontrol . the internal limit is determined by shifting v pcontrol down by a voltage equal to one diode drop (0.6 v typical) to account for the offset of the control voltage range. once this level is exceeded, the drive is turned off. c t is then dischar ged within t cpct(discharge) (maximum 500 ns) and held low until the beginning of the next switching cycle. this sequence is shown in figure 21. figure 21. on time generation pcontrol pct + ? pwm pdrv i pct(charge) t on v pcontrol ? 0.6 v t on v dd pdrv v pcontrol ct v pct since v pcontrol varies with the rms line voltage and output load, this naturally satisfies equation 6. if the values of compensation components are sufficient to filter out the bulk capacitor voltage ripple, the on time remains constant over the entire ac line cycle. the maximum on time of the controller occurs when v pcontrol is at its maximum value. therefore, c t must be sized to ensure that the required on time can be achieved at maximum output power and minimum input voltage. the maximum on time is calculated using equation 11. t on(max) c t v pct(max) i pct(charge) (eq. 11) where v pct(max) = 5 v (typical) and i pct(charge) = 210 a (typical). combining equation 11 with equation 6, results in equation 12. c t 2 p out l i pct(charge) vac ll 2 v pct(max) (eq. 12) where, vac ll is the minimum ac rms input voltage. off time control the off time varies with the instantaneous line voltage and is adjusted every cycle so that the inductor is demagnetized before the next switching cycle begins. the inductor is demagnetized once its current reaches zero. when this happens, the drain voltage begins to drop. this is detected by sensing the voltage across an inductor auxiliary winding. this winding, commonly known as a zero crossing detection (zcd) winding, provides the NCP1927 with a scaled version of the inductor voltage. figure 22 shows a typical zcd winding arrangement. figure 22. zcd winding implementation while the switch is on, a negative voltage appears at the pzcd pin. when the switch turns off, the zcd voltage swings positive, arming the zcd detector. the zcd voltage remains positive until the inductor current falls to zero and the inductor is demagnetized. the voltage then drops to 0 v and triggers the zcd detector to begin the next switch cycle. the arming threshold of the zcd detector is typically 1.4 v (v zcd(rising) ) and the triggering threshold is typically 0.7 v (v zcd(falling) ). the pzcd pin is internally clamped to v cl(pos) (typically 10 v) and v cl(neg) (typically ? 0.7 v). a resistor in series with the pzcd pin is required to limit the current into the pin and prevent it from exceeding 3 ma at v cl(pos) or ? 2 ma at v cl(neg) . figure 23 shows typical zcd waveforms.
NCP1927 http://onsemi.com 19 figure 23. voltage waveforms for zero current detection zcd winding v zcd(off) v zcd(on) v pdrv v drain v out v cl(pos) v zcd(rising) v zcd(falling) v cl(neg) v pzcd time time time time during startup, there are no zcd transitions to enable the pfc switch. a watchdog timer, t start , enables the pfc driver when no switch pulses are detected before it times out (180 s typical). the watchdog timer is also useful while operating at light load because the amplitude of the zcd signal may be too small to cross the zcd thresholds. frequency clamp since the NCP1927 operates in crm mode over the ac line half cycle, the switching frequency naturally increases as the line voltage approaches zero. in order to minimize the pfc inductor size, the NCP1927 features an internal oscillator that clamps the maximum switching frequency to f clamp (typically 385 khz). overvoltage/undervoltage protection the low bandwidth of the pfc stage feedback network causes it to have a slow transient response. this increases the risk of overshoots during transient conditions (startup, load steps, etc.). for safe operation, overvoltage protection (ovp) is utilized to prevent the output voltage from rising too high and overstressing the power stage components. the NCP1927 detects high v out levels and disables the driver until the output voltage returns to nominal levels. this protection keeps the output voltage within an acceptable range. while traditional pfc controllers often use one single pin for both under/overvoltage protections and feedback, the NCP1927 uses a dedicated pin for undervoltage protection (uvp) and ovp. this configuration allows the implementation of two separate feedback networks as shown in figure 24. figure 24. configuration with two separate feedback networks r pfb1 r pfb2 r povuv1 r povuv2 v out pfb povuv the double feedback configuration provides an increased level of safety , as it protects the pfc stage even if there is a failure of one of the two feedback arrangements. a 1 a (typical) current source, i uvp , pulls the povuv pin voltage below the uvp threshold if the pin is left floating to ensure the pfc stage will be protected. a comparator connected to the povuv pin provides the ovp protection. the output voltage that activates the ovp fault detection is calculated using equation 13. v out(ovp) v ovp r povuv1 r povuv2 r povuv2 i uvp r povuv1 (eq. 13) where v out(ovp) is the peak value of the output voltage including ripple and v ovp is the ovp threshold (2.5 v typical). when the ovp comparator is activated, the pfc driver is immediately turned off. once the feedback voltage drops below the hysteresis of v ovp (v ovp(hys) ), the pfc driver is re ? enabled. this helps to limit overshoots on the output during startup and transient loads. figure 25 depicts the operation of the ovp circuitry, while figure 26 shows the internal block diagram.
NCP1927 http://onsemi.com 20 figure 25. ovp timing diagram pdrv v out v out(nom) ovp time time time figure 26. povuv pin block povuv r povuv1 r povuv2 ovp uvp v uvp v ovp v out i uvp the NCP1927 detects a uvp fault when the output voltage falls below the uvp limit. during a uvp fault, the drive output and error amplifier (ea) are disabled, and c pcontrol is discharged. it is important to note that the pfc stage does not start if v povuv is lower than v uvp . this protects the application when there is a problem with the power path to the bulk capacitor (i.e. the capacitor is unable to charge up) or if the controller is unable to sense the output voltage (i.e. the povuv pin is floating). the output voltage that causes a uvp fault is calculated using equation 14. v out(uvp) v uvp r povuv1 r povuv2 r povuv2 i uvp r povuv1 (eq. 14) overcurrent protection (ocp) the NCP1927 contains an ocp circuit to protect the pfc stage by limiting the coil current. a current sense resistor (r sense ) is inserted in the return path to generate a negative voltage proportional to the coil current (v rsense ) as portrayed by figure 27. the circuit uses v rsense to detect when the coil current exceeds its maximum permissible level. to do so, the circuit incorporates an operational amplifier that sources the current necessary to maintain the pcs pin at zero volts. a resistor (r pcs ) inserted between the pcs pin and r sense allows the current sourced by the pcs pin (i pcs ) to be adjusted via equation 15. ? r sense i l r pcs i pcs 0 (eq. 15) where i l is the current flowing through the boost inductor. rearranging equation 15 allows i pcs to be calculated using equation 16. i pcs r sense r pcs i l (eq. 16) if i pcs exceeds i ocp (typically 250 a), an ocp condition is detected and the driver is turned off. the driver remains off until i pcs falls below i ocp , and the next zcd transition occurs or the watchdog timer expires. the maximum coil current (i l(max) ) is calculated with equation 17. i l(max) r pcs r sense i ocp (eq. 17) where i ocp is the ocp threshold current. figure 27. current sense block ? + to pdrv disable pcs i pcs > i ocp v dd r pcs i pcs r sense i pcs i l
NCP1927 http://onsemi.com 21 skip mode operation the NCP1927 automatically skips switching cycles when the power demand drops below a given level. this is accomplished by monitoring the internal offset pcontrol voltage. this voltage is compared to the pct ramp to control the power level in a particular design. during normal operation, the circuit generates the input line current necessary for matching the load power demand. if the need for power decreases, the regulation loop lowers the regulation voltage to reduce the power delivery accordingly. when the regulation voltage goes below a programmable pre ? set level, the pfc stage stops switching. this causes the output voltage to decrease, and the regulation voltage to increase. when the regulation voltage exceeds the skip threshold, switching resumes. this operation allows the pfc stage to deliver 10% power for 10% of the time, as opposed to 1% power for 100% of the time. this skip cycle mode, also called controlled burst operation, is much more efficient than a continuous power flow since it drastically reduces the number of switching pulses and their associated switching losses. to ensure stability, hysteresis is added. the pskip pin provides the possibility to adjust these levels by connecting it through a single resistor to ground. since the skip threshold power levels can vary with line voltage, they are calculated using equations 18 and 19. p skip(lower) v pskip 5v vac ll vac 2 p out(max) (eq. 18) p skip(upper) v pskip 4.5 v vac ll vac 2 p out(max) (eq. 19) where v pskip is the voltage applied to the pskip pin, vac ll is the minimum ac line voltage, vac is the operating line voltage, and p out(max) is the maximum output power. the skip pin voltage is adjusted through a resistor to ground using equation 20. v pskip i pskip r pskip (eq. 20) where i pskip is the value of the internal current source (30 a typical) and r pskip is the external resistor connected to ground. if desired, skip mode can be easily dis abled by connecting the pskip pin directly to ground. if the pskip pin is left floating, v pskip will rise towards the internal voltage rail and disable the drive. since the pcontrol pin is low during startup, the pfc skip mode is disabled until the pfc output reaches regulation and the ienable pin is high. a simplified schematic of the pskip pin is shown in figure 28. figure 28. schematic for pskip pin 9*r r pcontrol pfc_ok ota output pfault to pwm comparator skip pskip i pskip r pskip v dd
NCP1927 http://onsemi.com 22 go to standby pin the go to standby (gts) pin is used to disable the pfc stage during system standby based on the flyback stage load condition. this can be done by connecting it to the flyback stage feedback pin (ffb) through a resistor divider or by directly driving the pin with an optocoupler. these implementations are shown in figures 29 and 30. the gts pin contains an internal pull down resistor, r gts (typically 200 k ), for use with an optocoupler and to ensure the pfc is disabled if the pin is floating. figure 29. gts implementation with feedback pin gts ffb r gts1 r gts2 c gts the resistor divider from the ffb pin is used to setup the gts power level threshold. when v gts is brought below the gts threshold, v standby , the pfc controller stops switching and enter standby mode. it remains in standby until v gts is brought above the hysteresis of v standby (v standby(hys) ). a timer is included on the gts pin to ensure transients on the flyback converter do not trigger gts. however, the pfc must come out of standby as soon as possible if there is a request to turn on the tv. therefore, the timer is bypassed when coming out of standby. the ffb voltage at which the pfc enters gts is expressed using equation 21. v ffb(gts) v gts r gts1 r equiv r equiv (eq. 21) where r equiv is the parallel resistor combination of r gts and r gts2 and is calculated using equation 22. r equiv r gts r gts2 r gts r gts2 (eq. 22) if direct control of the pfc standby mode is desired, the gts pin can instead be driven with an optocoupler from the secondary side to force the pfc stage in and out of standby mode. a resistor (r limit ) is placed in series with the optocoupler to limit the current into the gts pin. figure 30. gts implementation with optocoupler vcc_aux gts c gts from secondary side r limit ienable pin the ienable pin is designed to drive an optocoupler that enables the flat panel tv backlight inverter once the pfc stage reaches regulation. the NCP1927 achieves this by monitoring the current sourced by the ea. once this current drops to 0 a, the ienable pin voltage switches to v ienable(high) (typically 5.0 v). this operation is shown in figure 31. figure 31. ienable pin timing time v out v out(max) time v ienable 5 v 0 v v out(min) v out(nom) time i ea(out) 0 a ? 20 a inverter starts undershoot from inverter load a separate comparator on the pfb pin is used to protect the inverter from undervoltage conditions by detecting when the pfb voltage falls below v disable . when this occurs, the ienable pin voltage switches to v ienable(low) . using the result from equation 7, the output threshold that sets the ienable pin low can be calculated with equation 23. v out(disable) v out v disable v ref (eq. 23) where v disable is the disable threshold (1.865 v typical). the ienable pin can also be used as a voltage reference. to filter noise, a decoupling capacitor (c ref ) may be connected to the pin.
NCP1927 http://onsemi.com 23 package dimensions soic ? 16 case 751b ? 05 issue k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 18 16 9 seating plane f j m r x 45 g 8 pl p ? b ? ? a ? m 0.25 (0.010) b s ? t ? d k c 16 pl s b m 0.25 (0.010) a s t dim min max min max inches millimeters a 9.80 10.00 0.386 0.393 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019 6.40 16x 0.58 16x 1.12 1.27 dimensions: millimeters 1 pitch soldering footprint* 16 89 8x *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 NCP1927/d soft ? skip is a trademark of semiconductor components industries, llc (scillc). literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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